Networks on Chip, router architectures and performance challenges

With the continuous technology scaling, System On Chips (SoCs) have evolved considerably and can integrate an important number of Intellectual Property (IP) cores in the same chip. However, global interconnects are become the main performance limitation of SoCs. The Network on Chip (NoC) paradigm has emerged as an efficient interconnection structure addressing the global wire delay problem. This solution outperforms traditional on chip interconnects, such as Point to Point (P2P) links, busses and bridges. Since the introduction of the NoC paradigm in the last decade, several methodologies have been presented by researchers to enhance its performances in terms of latency, area occupancy and power consumption. In this paper we described the interconnect evolution from point to point links to network on chip paradigm. Then, we focused on the NoC concept and presented some of their principal characteristics. Finally, we proposed a new switch architecture enabling an adaptive interport buffers sharing. The proposed design optimizes the virtual channels exploitation which results in an improvement of the NoC zero load latency and throughput without inducing neither area nor power consumption overhead.